Computer Organisation and Architecture MCQ Questions and Answers Part – 1
Computer Organisation and Architecture MCQ Questions and Answers Part – 2
Computer Organisation and Architecture MCQ Questions and Answers Part – 3
51. Many OS enable the CPU to proceeds a number of independent programs concurrently called ____________ .
A. multitasking.
B. multiprogramming.
C. multi processing.
D. multiple functions.
ANSWER: B
52. RAM stands for _________.
A. random access memory.
B. random memory.
C. read only memory.
D. read access memory.
ANSWER: A
53. The map for boolean functions of 4 variables consist of _______.
A. 4 minterms.
B. 4 maxterms.
C. 16 minterms.
D. 16 maxterms.
ANSWER: C
54. RAM is _______________ its contents are destroyed when power is turned off.
A. non volatile.
B. permanent.
C. volatile.
D. initial.
ANSWER: A
55. Initial program is stored in ROM portion of main memory called _____________ loader.
A. linking.
B. volatile.
C. non volatile.
D. bootstrap.
ANSWER: D
56. A tract in magnetic disk in a given sector near the circumstance is ________ than near the centre.
A. smaller.B. longer.
C. thinner.
D. bigger.
ANSWER: B
57. A disk drive with removable disks is called _____________ disk.
A. magnetic tape.
B. magnetic.
C. floppy.
D. record.
ANSWER: C
58. Which of the following combinational circuit selects binary information from one of many input lines
and directs it to a single output line?
A. Encoder.
B. Decoder.
C. Demultiplexer.
D. Multiplexer.
ANSWER: D
59. The transformation of date from main memory to cache memory is called ____________ process.
A. execution.
B. mapping.
C. unmapping.
D. loading.
ANSWER: B
60. The basic component of arithmetic circuit is________.
A. parallel subtractor.
B. parallel adder.
C. half adder.
D. full adder.
ANSWER: B
61. The micro operation that specifies binary operations for strings of bits stored in registers
are___________.
A. logic micro operation.
B. shift micro operation.
C. arithmetic micro operation.
D. register transfer micro operation.
ANSWER: A
62. The addition and subtraction operations can be combined into one common circuit by including a
_______________ gate with each full adder.
A. exclusive-OR.
B. AND.
C. OR.
D. NAND.
ANSWER: A
63. The name of the operation that complements bits in A register where there are corresponding 1’s in B
register is _______.
A. selective set.
B. selective complement.
C. selective clear.
D. mask.
ANSWER: B64. LIFO stands for _______________.
A. last in flag out.
B. last in first out.
C. loop in first out.
D. loop in flag out.
ANSWER: B
65. The storage devices that stores information in a manner that the item stored last in first item retrieved
is__________.
A. queue.
B. stack.
C. CPU.
D. register.
ANSWER: B
66. The operation of deletion in stack is____________.
A. PUSH.
B. POP.
C. FRONT.
D. REAR.
ANSWER: B
67. SP stands for _____________.
A. Storage Pointer.
B. Seek Pointer.
C. Stack Pointer.
D. Synchronous Pointer.
ANSWER: C
68. The expansion of RPN is ____________.
A. Reverse Polish Notation.
B. Review Polish Notation.
C. Reverse Pointer Notation.
D. Review Pointer Notation.
ANSWER: A
69. The notation A+B is ______________.
A. prefix notation.
B. postfix notation.
C. infix notation.
D. none of these.
ANSWER: C
70. The bits of the instruction are divided into groups called______________.
A. formats.
B. fields.
C. bytes.
D. address.
ANSWER: B
71. ADD R1, A, B is_______________.
A. zero address instruction format.
B. one address instruction format.
C. two address instruction format.
D. three address instruction format.
ANSWER: D
72. RISC stands for_____________.A. Reduced Instruction Set Computer.
B. Reverse Instruction Set Computer.
C. Reduced Implied Set Computer.
D. Reverse Implied Set Computer.
ANSWER: A
73. The mode in which the effective address is equal to the address part of instruction is ______.
A. indirect addressing mode.
B. direct addressing mode.
C. register addressing mode.
D. relative addressing mode.
ANSWER: B
74. The instruction that performs arithmetic, logic and shift operations are____________.
A. data transfer instruction.
B. data manipulation instruction.
C. register transfer instruction.
D. program control instruction.
ANSWER: B
75. SISD stands for_____________.
A. Single Instruction stream, Single Data stream.
B. Simple Instruction stream, Simple Data stream.
C. Stack Instruction stream, Stack Data stream.
D. Storage Instruction stream, Storage Data stream.
ANSWER: A
76. The instruction provides decision making capabilities are___________.
A. data transfer instruction.
B. data manipulation instruction.
C. register transfer instruction.
D. program control instruction.
ANSWER: D
77. The ____________ contains an address to specify the desired location in the memory.
A. word count register.
B. address register.
C. control register.
D. none of the above.
ANSWER: B
78. MISD means______________.
A. Multiple Instruction stream, Single Data stream.
B. Memory Instruction stream, Single Data stream.
C. Multiple Instruction stream, Storage Data stream.
D. Memory Instruction stream, Storage Data stream.
ANSWER: A
79. DR stands for_______________.
A. Direct Register.
B. Data Register.
C. Division Register.
D. Decrement Register.
ANSWER: B
80. Which counter counts in binary-coded decimal from 0000 to 1001 and back to 0000?
A. BCD counter.
B. Asynchrounous counter.C. Flip-flop.
D. Register.
ANSWER: A
81. The computer code for interchanging the information between terminals is___________.
A. ASCII.
B. BCD.
C. EBCDIC.
D. CDIE.
ANSWER: A
82. A byte consists of____________.
A. one bit.
B. four bits.
C. eight bits.
D. sixteen bits.
ANSWER: C
83. The notation AB+ is____________.
A. prefix notation.
B. postfix notation.
C. arithmetic notation.
D. infix notation.
ANSWER: B
84. The field that specifies the way the operand or the effective address is determined is ____________.
A. processor field.
B. mode field.
C. operation code field.
D. address field.
ANSWER: C
85. The NOT gate is also called __________.
A. AND gate.
B. NAND gate.
C. XOR gate.
D. Inverter.
ANSWER: D
86. TOS represents______________.
A. Top Of Simulator.
B. Top Of Stack.
C. Top Of Storage.
D. Top Of System.
ANSWER: B
87. The 10’s complement of a decimal number is equal to its _____________.
A. 9’s complement + 1.
B. 9’s complement – 1.
C. 8’s complement + 2.
D. 8’s complement – 2.
ANSWER: A
88. AR represents____________.
A. Auto Register.
B. Address Register.
C. Auxiliary Register.
D. Associate Register.ANSWER: B
89. The addressing mode where the controls of an index register is added to the address part of the
instruction_____.
A. relative addressing mode.
B. direct addressing mode.
C. indexed addressing mode.
D. immediate addressing mode.
ANSWER: B
90. The instructions that perform binary operations on strings of bits stored in registers_______.
A. logical instructions.
B. shift instructions.
C. arithmetic instructions.
D. complement instructions.
ANSWER: A
91. The term that provides simultaneous data processing tasks are____________.
A. parallel processing.
B. array processing.
C. vector processing.
D. distributed processing.
ANSWER: A
92. The ________ holds the number of words to be transferred to the memory.
A. word count register.
B. address register.
C. control register.
D. program register.
ANSWER: A
93. BCD represents_______.
A. Binary Coded Decimal.
B. Binary Coded Data.
C. Binary Computational Decimal.
D. Binary Computational Data.
ANSWER: A
94. The NOR gate produce the output 1, if _______.
A. X = Y = 0.
B. X=1, Y=0.
C. X=0, Y=1.
D. X = Y = 1.
ANSWER: A
95. In half adder, carry will be 1, when ________.
A. X = Y = 0.
B. X=0, Y=1.
C. X=1, Y=0.
D. X = Y = 1.
ANSWER: D
96. The expansion of BCD is ________________.
A. Binary Codiac Decimal.
B. Binary Coded Decimal.
C. Binary Coded Digit.
D. Binary Codiac Digit.
ANSWER: B97. What is the Excess 3 code for the binary equivalent 8?
A. 1011.
B. 1100.
C. 1101.
D. 1111
ANSWER: A
98. The base or radix of octal number system is _______________
A. 2.
B. 16.
C. 10.
D. 8.
ANSWER: D
99. The base or radix of hexadecimal number system is _____________
A. 2.
B. 16.
C. 10.
D. 8.
ANSWER: B
100. The flip flop used to synchronize the state change during a clock pulse transition is ___________
A. JK flip flop.
B. T flip flop.
C. edge triggered flip flop.
D. RS flip flop.
ANSWER: C
